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MIPS-Robot

It's been nearly 4 years since Imagination Technologies acquired MIPS Technologies, the developers of the MIPS architecture. Over that time, Imagination has fabricated a concerted endeavor to scale its MIPS CPU architectures outward and upwards to support a wider assortment of workloads, utilise-cases, and capabilities. MIPS was one time a high-end architecture that powered workstations and loftier performance computers, only its stronghold today is in the embedded market. The I6500 could change that, and the core has already been tapped to drive the hereafter (pun-intended) of self-driving auto technology.

Commencement, let's talk about the core. The I6500 and I6400 share the aforementioned basic CPU compages. Both chips are dual-upshot processors with support for simultaneous multi-threading (SMT). Both can handle up to four threads per CPU core, offering an optional SIMD/FPU implementation with 128-bit registers (broadly equivalent to ARM'due south NEON, though the item implementation details may vary), hardware virtualization back up, and a sixteen-way associative L2 cache that can calibration up to 8MB.

mips-i6400-cpu-block-diagram-F

What sets the I6500 apart from the earlier I6400 is its support for large-scale cluster deployments and heterogeneous compute integration. Where the I6400 targets multi-core applications, the I6500 is meant to be used every bit part of a multi-cluster system with potential support for hundreds of CPUs, equally well as other heterogeneous compute accelerators.

I6500_diagram_Oct16

Imagination is dividing the chip'due south heterogeneous capabilities into ii segments — "heterogeneous inside" and "heterogeneous exterior." "Heterogeneous within," according to Imagination, refers to how customers can optimize the I6500 core in a number of ways, including altering its simultaneous multi-threading configuration, irresolute the L1 cache size, including or excluding the SIMD/FPU unit of measurement, calculation up to 1MB of Information ScratchPad RAM, calculation upwardly to 4 AXI ports to connect with low-latency peripherals, and tweaking dynamic voltage and frequency settings on a per-cadre footing. This isn't really heterogeneous computing as AMD has defined it, merely it does speak to how the I6500 is an extremely flexible core design.

"Heterogeneous exterior," more closely resembles HSA as we've seen it used by AMD and Qualcomm. MIPS writes:

The capabilities of the I6500 family unit extend even farther on the "heterogeneous outside" framework through a unique feature supporting the build of "accelerator only" cluster(s). A single cluster of the I6500 family platform can actually be configured for having up to eight IO coherence units (IOCUs) connected together, with no CPU in the cluster.

Custom-designed or third party functional accelerators can be connected via standard AXI4 interface to these IOCU ports, providing very localized and concentrated compute resources for specific tasks or applications. Such a configuration provides benefits to a cluster of functional accelerators by utilizing a localized, shared low latency L2 cache amid the accelerator units. Information technology concentrates the processing and traffic of the accelerators and the CPUs into carve up clusters.

I6500-block-diagram-3

In this way in that location is less competing traffic and bandwidth allocation to the respective L2 enshroud memories for each processing cluster –all the while maintaining memory coherency betwixt the respective L2 caches.

An of import design win

When Imagination Technologies bought MIPS, it entertained some hope of winning space in the Android market. This largely didn't happen — ARM just had as well much of a head commencement for MIPS to make much headway. A newly announced deal with assisted driving company Mobileye may give MIPS's licensing business a serious heave in the future. Mobileye will be tapping the visitor's I6500 to power their upcoming EyeQ5 assisted driving system, which is currently expected to hit the market place in 2022. The EyeQ5 volition have eight MIPS processors combined with Mobileye's own Vision Processors for image recognition and navigation, PCWorld reports.

There's no word even so of any big-fe or other large-calibration cluster compute efforts around the I6500, but the Mobileye bargain could be pregnant on its own. Mobileye provides technology to multiple companies (it recently parted ways with Tesla in a loftier-profile disagreement over the nature of the Tesla Autopilot program). MIPS CPUs are technically compatible with Linux and Android, but oasis't been the focus of the same developer attending as ARM, which dominates the non-x86 market for CPUs.